From: Ard Biesheuvel
maillist inclusion
commit e2aa765c4eb9bbcdd3046744e6f73050d1175138
category: feature
feature: ARM kaslr support
issue: #I3ZXZF
CVE: NA
Reference: https://git.kernel.org/pub/scm/linux/kernel/git/ardb/linux.git/commit/?h=arm-kaslr-latest&id=e2aa765c4eb9bbcdd3046744e6f73050d1175138
-------------------------------------------------
This replaces a few copies of the open coded calculations of the
physical address of 'pen_release' in the secondary startup code
of a couple of platforms. This ensures these quantities are invariant
under runtime relocation.
Cc: Russell King
Acked-by: Nicolas Pitre
Signed-off-by: Ard Biesheuvel
Signed-off-by: Cui GaoSheng
Reviewed-by: Xiu Jianfeng
Signed-off-by: Chen Jun
Signed-off-by: Yu Changchun
---
arch/arm/mach-prima2/headsmp.S | 11 +++--------
arch/arm/mach-spear/headsmp.S | 11 +++--------
arch/arm/plat-versatile/headsmp.S | 9 +--------
3 files changed, 7 insertions(+), 24 deletions(-)
diff --git a/arch/arm/mach-prima2/headsmp.S b/arch/arm/mach-prima2/headsmp.S
index 88ea1243942a..e09dcaca320e 100644
--- a/arch/arm/mach-prima2/headsmp.S
+++ b/arch/arm/mach-prima2/headsmp.S
@@ -8,6 +8,8 @@
#include
#include
+#include
+
/*
* SIRFSOC specific entry point for secondary CPUs. This provides
* a "holding pen" into which all secondary cores are held until we're
@@ -16,10 +18,7 @@
ENTRY(sirfsoc_secondary_startup)
mrc p15, 0, r0, c0, c0, 5
and r0, r0, #15
- adr r4, 1f
- ldmia r4, {r5, r6}
- sub r4, r4, r5
- add r6, r6, r4
+ adr_l r6, prima2_pen_release
pen: ldr r7, [r6]
cmp r7, r0
bne pen
@@ -30,7 +29,3 @@ pen: ldr r7, [r6]
*/
b secondary_startup
ENDPROC(sirfsoc_secondary_startup)
-
- .align
-1: .long .
- .long prima2_pen_release
diff --git a/arch/arm/mach-spear/headsmp.S b/arch/arm/mach-spear/headsmp.S
index 96f89436ccf6..32ffc75ff332 100644
--- a/arch/arm/mach-spear/headsmp.S
+++ b/arch/arm/mach-spear/headsmp.S
@@ -10,6 +10,8 @@
#include
#include
+#include
+
__INIT
/*
@@ -20,10 +22,7 @@
ENTRY(spear13xx_secondary_startup)
mrc p15, 0, r0, c0, c0, 5
and r0, r0, #15
- adr r4, 1f
- ldmia r4, {r5, r6}
- sub r4, r4, r5
- add r6, r6, r4
+ adr_l r6, spear_pen_release
pen: ldr r7, [r6]
cmp r7, r0
bne pen
@@ -37,8 +36,4 @@ pen: ldr r7, [r6]
* should now contain the SVC stack for this core
*/
b secondary_startup
-
- .align
-1: .long .
- .long spear_pen_release
ENDPROC(spear13xx_secondary_startup)
diff --git a/arch/arm/plat-versatile/headsmp.S b/arch/arm/plat-versatile/headsmp.S
index 09d9fc30c8ca..cec71853b0b3 100644
--- a/arch/arm/plat-versatile/headsmp.S
+++ b/arch/arm/plat-versatile/headsmp.S
@@ -18,10 +18,7 @@ ENTRY(versatile_secondary_startup)
ARM_BE8(setend be)
mrc p15, 0, r0, c0, c0, 5
bic r0, #0xff000000
- adr r4, 1f
- ldmia r4, {r5, r6}
- sub r4, r4, r5
- add r6, r6, r4
+ adr_l r6, versatile_cpu_release
pen: ldr r7, [r6]
cmp r7, r0
bne pen
@@ -31,8 +28,4 @@ pen: ldr r7, [r6]
* should now contain the SVC stack for this core
*/
b secondary_startup
-
- .align
-1: .long .
- .long versatile_cpu_release
ENDPROC(versatile_secondary_startup)
--
2.22.0
